Convolution encoder RTL design

The main aim of a digital communication system is to transmit information reliably over a channel. The available amount of transmitter power and bandwidth are the major constraints in the design of a digital communication system. The channel can be coaxial cables, microwave links, or fiber optic. The channel is subject to various types of noise, distortion, and interference. Also some communication systems have limitation on transmitter power. All these may lead to errors. Consequently we may need some form of error control encoding to recover the information reliably. Convolution codes are extensively used for real time error correction.

The purpose of forward error correction (FEC) is to improve the capacity of a channel by adding some carefully designed redundant information to the data being transmitted through the channel. The process of adding this redundant information is known as channel coding. Convolution codes operate on serial data, one or a few bits at a time. Block codes operate on relatively large (typically, up to a couple of hundred bytes) message blocks. There are a variety of useful convolution and block codes, and a variety of algorithms for decoding the received coded information sequences to recover the original data.

The task of channel coding is to encode the information sent over a communication channel in such a way that in the presence of channel noise, errors can be detected and/or corrected.

The term rate = no of inputs bits / no of output bits , let rate is 1/2 means input is 1 bit and encoder has 2 output bits. for understanding we take 1/2 rate for design. Second important term is constrain length which define the how many shift elements used in encoder also it has that number of bit history which helps in correcting the error bits at the receiver side.But the trellis size also depend on constrain length, also higher length means complex design at the receiver for decoding.

The convolution encoder is basically a finite state machine. The K bit input is fed to the to the constrain length K shift register and the n output are calculated from the generator polynomial by the Modulo-2 addition.

This is 1/2 rate Convolution encoder, it build from dff and xor gate. And its state table as below.

s1 s0 is dff outputs and v1 v2 is xor gate output, in trellis form it looks like this,

both are same trellis in different color or format, let it be it doesn’t matter. the first 4 circle is present state and next 4 is next state , and every state has two possible inputs like 0/1. it drown by 2 lines from each state, and each line is mark by x/xx, which means, input bit / output of xor gates. hope you will get it .

above trellis shown when msg bits 00110100 is enter into encoder , all msg bits terminated by some termination bits, you can ref more for this point from else where.

this is the technology view for alter vendor, it is petty old from my rusty disk, i think for cyclone series.

for sequence d=101101010

additional , encoding sequence 0110 to the encoder and its output sequence is 00 11 01 01 it shown by the dark green line in trellis diagram.

this for ref example with state table and its trellis and sequence of msg bits, for two different encoder of different architecture design, it is only for ref. this is my handwritten diagram for your ref. hope it will help you to get the idea of it,

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