Pre-Post rtl simulation a case study
The point is that i am not good skill writer/editor, but still some one may find this article useful, please excuse if any differences you found, also make comment for…
SpyGlass CDC review test 1
To have review for spyglass cdc, first we need code, here i attached 2 codes 1] cdc_test2.v is top 2] clk_rst_unit1.v is for clk and clk div and reset logic.…
HDL code Linting first review test
With what i need to start ? this is main question, let me put my opinion about it, means about linting. It is a process to find the potential error,…
Convolution encoder RTL design
The main aim of a digital communication system is to transmit information reliably over a channel. The available amount of transmitter power and bandwidth are the major constraints in the…
FIFO DEPTH CALCULATION
The communication between the two modules, which is operating at different clock speed. To ensure the lossless data transfer, there are few methods thro which we can make it happens.…
Static Timing Analysis STA in vlsi
For going in to more details, take a look of notations that are used in this blog. 1] tc2q – clock to q of filp-flop …
FIR digital filter RTL design
Here our focus is on FIR digital filter, IIR filter not a practical filter so we left for discussion. For the experiment we are consider direct form, you can used…
AC lamp-fan control dimmer circuits
From the years, we are seen lots of dimmer circuits for AC and DC as well, the circuits that mostly peoples are using traditionally and what other advance chips are…
Fixed and floating point RTL compare
Here in this blog, the float and fix based add and multiple unite conspire based on the LUT consumption. For the farther quires and help please leave comment or pm…
Hardware implementation of Multirate DSP blocks
In this blog post we look more close to DSP multirate hardware implementation of main four blocks. 1] Downsample Block downsample(x,n) 2] Upsample Block upsample(x,n) 3] Decimation Block decimate(x,n) […